The present invention relates to divider circuits, and in particular, to circuits and methods that may be used to implement frequency division using in-phase and quadrature signals.
Electronic systems often have many different components that include voltage or current signals that have different frequencies. It is often desirable to modify the frequencies of such signals as the signals are used to perform different tasks. One common modification to a signal is frequency division. Frequency division is the process of dividing a signal's frequency by some value (e.g., an integer or fraction). Circuits that perform frequency division are referred to as “Dividers” and are found in a wide variety of electronic applications.
FIG. 1 illustrates a prior art divider circuit. A divider circuit 100 receives an input signal, Vin, and generates an output signal, Vout. The input signal, Vin, may be a square wave, for example, having a period, T1, and a corresponding frequency, F1=1/T1. The output signal, Vout, of divider circuit 100 may have some frequency that is less than the frequency of the input signal, Vin. For example, the output signal, Vout, may have a period, T2, that is twice the value of the input signal period, T1, and thus the output frequency, Fout, has a frequency that is one-half the frequency of the input signal, Vin.
FIG. 2 illustrates a prior art D-Flip Flop divider circuit. The circuit includes two D-flip flops (“DFF”) 201 and 202 connected in series. In this example, each DFF has differential inputs (+in, −in), differential outputs (+out, −out) and differential clock inputs (CK and CK). DFF 201 will load data at its input (i.e., from DFF 202) on the rising edge of CK. Similarly, DFF 202 will load data at its input (i.e., from DFF 201) on the falling edge of CK, which is the rising edge of CK. Thus, each DFF output will transition between logic states once for every period of CK. Consequently, the period of each DFF output is twice the period of the clock, and the output of the divider has one-half the frequency of the clock. The output of the circuit may be taken from either DFF 201 (i.e., +OUT1_DIV2 and −OUT1_DIV2) or DFF 202 (i.e., +OUT2_DIV2 and −OUT2_DIV2). DFFs 201 and 202 have, thus, divided the clock frequency by two. Such a circuit is one example of a divide-by-two circuit.
One problem associated with prior art divider circuits is that typically only one of the output pairs of the divider are used to drive subsequent stages in the system. FIG. 3 illustrates a prior art approach used for series connected divider circuits. Circuit 300 includes a first divider circuit 301 receiving differential clock inputs and using one of the differential outputs to drive a second divider circuit 302. If only one pair of divider outputs is used to drive subsequent stages, the DFF circuits in the divider will not be subject to equal loading. Such load imbalances may cause degradations in the circuit's behavior and performance. One prior art approach to balancing the circuit is to use a “replica dummy load” 303. Replica circuit 303 is typically a circuit that replicates the loading effects of the active circuit connected to the active outputs of divider 301, but does not process any signals and has no other purpose except to provide load balancing. While such circuits are useful for load balancing, they are disadvantageous because they can consume additional power and take up additional area on an integrated circuit, thereby reducing efficiency and increasing the cost.
Another problem associated with prior art divider circuits is that the internal operating parameters of the system are often not working efficiently to achieve the desired results. Fig 4A illustrates a prior art implementation of a circuit 400 that may be used in a divider circuit. Circuit 400 includes a differential pair 401 and a cross-coupled pair 402 that are coupled together at a common load. Circuit 400 receives differential clock inputs at transistors M1 and M2. When the circuit is connected in a divide-by-two configuration with another similar circuit, the inputs +in1 and −in1 will be received on the gate terminals of transistors M3 and M4. Differential pair 401 and cross-coupled pair 402 will generate currents i1 and i2. Fig 4B illustrates the currents i1 and i2 in the circuit of FIG. 4A. In many applications, it is desirable to design a circuit such that these currents are operating at an optimum for the particular system in which such circuit is used. If these currents are not designed efficiently, for example, the circuit and system in which it is used may not perform as well. This problem is particularly important in high frequency applications.
Thus, there is a need for improved divider circuits, and in particular, for improved circuits and methods that may be used to implement frequency division using in-phase and quadrature signals.